1. Field of the Invention
The present invention generally relates to circuits for generating a clock signal of a desired frequency, and particularly relates to a clock shift circuit which changes a clock signal from a given frequency to another frequency.
2. Description of the Related Art
In large-scale logic circuits such as semiconductor integrated circuits, a technology for controlling the supply of clock signals inside a circuit as circumstances demand is becoming increasingly important for the purpose of cutting down power consumption. Especially in portable equipment for which power consumption is an important issue, such technology is widely used.
Conventionally, the control of start/stop of clock supply is not taken care of by the system. In a general configuration, the start/stop of clock supply is made simply in response to power-on and power-off. With the widespread use of portable equipment and an increase in circuit size, standby power consumed by load capacitance associated with clock signal lines can no longer be disregarded, making it necessary to control the start/stop of clock signals.
When a transition is made from a clock active state using a normal operating frequency to a clock suspended state such as a standby state, or when return from the clock suspended state is made, a clock generally comes to a sudden stop or makes a sudden start to immediately oscillate at the normal operating frequency. When a clock is suddenly changed in such a manner, circuitry that uses the clock generates a sudden change in the consumption of electric currents. This may cause regulators inside semiconductor integrated circuits to generate abnormal voltages.
Because of this, it is desirable to change clock frequency gradually between the clock active state using the normal operating frequency and the clock suspended state. To this end, a clock generating circuit with the function to switch clock frequencies is required, an example of which is disclosed in Patent Documents 1 through 3.
A circuit taught by Patent Document 1 includes an oscillator that operates at high speed, a decimated clock circuit that outputs a plurality of decimated clocks, and a frequency divider. The decimated clock circuit generates a set of base frequencies, and the frequency divider divides the frequencies for outputting.
In Patent Document 2, an image recording apparatus includes a decimating means for decimating an original clock supplied from an original clock generating means, and a frequency dividing means for dividing the decimated clock by a fixed division rate for outputting as a pixel clock for image recording purposes.
In Patent Document 3, provision is made to divide an original clock by frequency division rates responsive to power supply voltage. By using a large number of bits or increasing the number of the frequency division rates, the original clock can be divided by an increased number of frequency division rates, without the addition of a frequency division circuit to hardware.
[Patent Document 1] Japanese Patent Application Publication No. 2000183729.
[Patent Document 2] Japanese Patent Application Publication No. 2001-213002.
[Patent Document 3] Japanese Patent Application Publication No. 2002-202829.